The present invention relates to a semiconductor memory device, more particularly to a positive charge pumping circuit for generating a high voltage, for instance 13 volts, using a low power supply voltage, for example 3 volts or 5 volts, in a non-volatile memory device such as flash EEPROM.
Generally, in a semiconductor memory device, if there is required the higher voltage than the power supply voltage VCC which is applied from outside of the semiconductor memory device chip, it should be generated in the chip. For this generating, a positive charge pumping circuit is used.
FIG. 1 is a circuit diagram of a conventional positive charge pumping circuit, through which the prior art and its problem will be explained.
Referring to FIG. 1, the conventional positive charge pumping circuit includes a plurality of MOS transistors 12 and 13, and a plurality of MOS transistors 14 and 15 and it performs a positive pumping from the power supply voltage VCC to the required potential VPP (e.g. 12 volts). For a plurality of MOS transistor 12 and 13, the drain-source paths thereof are coupled in series between the power supply potential VCC and the pumping potential VPP and each is diode-connected where each gate and source thereof is coupled together. Here, the connection nodes between the plurality of MOS transistors 12 and 13 constitutes a plurality of pumping line nodes PN1 and PN2. In the plurality of MOS transistors 14 and 15, each has capacitor-connection, that is, the source and the drain of the transistor 14 or 15 are coupled together, in which the common source/drain is applied with corresponding clock CLK1 or CLK2 and the gate is coupled to corresponding pumping line nodes PN1 or PN2.
However, in this conventional positive charge pumping circuit, since the driving potential as much as the depth of VCC is applied to the driving transistors (that is, the MOS transistors 14 and 15) by the clocks CLK1 and CLK2 which are swung between the power supply potential VCC and the ground, many stages of diode-connected MOS transistors and capacitor-connected MOS transistors are needed to provide the desired potential VPP. This results in that the sheet resistance generated at the respective stages and the respective threshold voltage loss are increased in proportion to the number of the stages, which in turn the efficiency thereof is deteriorated.
In other words, if the VCC is 5 volts and the threshold voltage Vt is 2 volts, while the pumping line nodes PN1 and PN2 are primarily boosted by 5 volts due to the operation of the driving capacitive MOS transistors 14 and 15, only 3-volt boosting is transferred to the next upper stages PN1 and VPP because of the potential-drop of the threshold voltage Vt of the diode MOS transistors 12 and 13. Thus a four stage pumping is required in order to provide the desired 12 volts.
The above-mentioned sheet resistance also causes the problem in that the current transfer speed of the pumping circuit is reduced.